Questions

13.50 It is required to find the input resistance and the voltage gain of the input stage shown in Fig. 13.18. Let VICM ≪ 0.8 V so that the Q3−Q4 pair is off. Assume that Q5 supplies 8 µA, that each of Q7 to Q10 is biased at 8 µA, and that all four cascode transistors are operating in the active mode. The input resistance of the second stage of the op amp is 1.5 MΩ. The emitter-degeneration resistances are R7 = R8 = 22 kΩ, and R9 = R10 = 33 kΩ. [Hint] 125 k; 95.4 V/V

1 viewsvenkyelectrical Asked question 22 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.49 For the circuit in Fig. 13.17, let VCC = 3V, VBIAS = 0.7 V, and IC6 = 40 µA. Find RC that results in a differential gain of 14 V/V. What is the input common-mode range and the input differential resistance? Ignore base currents except when calculating Rid. If Rid is to be increased by a factor of 4 while the gain and VICM remain unchanged, what must I and RC be changed to?

1 viewsvenkyelectrical Asked question 23 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.48 For the circuit in Fig. 13.16, let VCC = 3 V, VBIAS = 2.3 V, I = 20 µA, and RC = 35 kΩ. Find the input common-mode range and the differential voltage gain vo/vid. Neglect base currents.

1 viewsvenkyelectrical Asked question 23 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.47 (a) Find the input common-mode range of the circuit in Fig. 13.15 assuming R1 = 0 and the current source I1 is simply a pnp transistor biased in active mode with VCC = 3V. (b) Give the complementary version of the input stage in Fig. 13.15; that is, the one in which the differential pair is npn. For the same conditions as in (a), what is the input common-mode range? (a) 0.1 V ≤ VICM ≤ 2.2 V; (b) 0.8 V ≤ VICM ≤ 2.9 V

1 viewsvenkyelectrical Asked question 24 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.46 For the op-amp circuit in Fig. 13.15, assume that VCC = 5V, |VBE| = 0.6 V for all transistors, and R2 = 300 Ω. Also assume that the current source I2 = 200 µA requires a voltage drop of at least 0.3 V to operate properly. Find the resulting limits on the output swing.

1 viewsvenkyelectrical Asked question 24 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.45 Design a Widlar current reference to generate the bias currents I1 and I2 of the op amp in Fig. 13.15. Use the circuit of Fig. 13.14 (excluding transistors Q5 and Q6) with I = 15 µA, I7 = 45 µA, and I8 = 150 µA. Assume IS1,3,4 = 10−15 µA and IS2 = 4 × 10−15. Specify the areas of Q7 and Q8 in terms of the area of Q3 and all resistor values. Design for a voltage drop of 0.1 V across R3 and R4. A7 = 3A3; A8 = 10A3; R3 = R4 = 6.67 kΩ; R7 = 2.22 kΩ; R8 = 667Ω

1 viewsvenkyelectrical Asked question 25 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.44 The resistors R1 in Fig. 13.15 are mismatched so that one has a value R1 + ∆R1. You may assume that the base currents are negligible.

1 viewsvenkyelectrical Asked question 25 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.43 Consider the current-mirror active load Q3,4 in the two-stage op amp of Fig. 13.15 with R1 = 400 Ω. What value must R1 be increased to in order to increase its output resistance by a factor of 2? Assume that I1 = 50 μA and all transistors have β = 200 and VA = 125 V. 1.8 k

1 viewsvenkyelectrical Asked question 26 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.42 It is required to use the current I5 in Fig. 13.14 to bias an npn differential pair. The transistor Q5 is identical to Q2, and R5 is equal to R2. The differential pair has two equal collector resistances RC connected to VCC, and the output voltage vO is taken between the two collectors. (a) Find an expression for the differential gain Ad in terms of (RC/R5) and (IS5/IS1). Comment on the expected temperature dependence of Ad. Neglect the effect of finite βN. (b) Specify the values of R5 and RC required for I = 20 µA and Ad = 6 V/V. Let the emitter areas of Q1 and Q5 be in the ratio 1:4.

1 viewsvenkyelectrical Asked question 27 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.41 Consider the circuit of Fig. 13.14 for the case designed in Exercise 13.14, namely, I = 10 µA, IS2/IS1 = 2, R2 = 1.73 kΩ, R3 = R4 = 20 kΩ. We must generate constant currents of 10 µA and 40 µA in Q5 and Q6, respectively. What should the emitter areas of Q5 and Q6 be relative to that of Q1 with R5 = R6 = 0? What value of a resistance R6 will, when connected in the emitter of Q6, reduce the current generated by Q6 to 10 µA? Assuming that the VBIAS1 line has a low incremental resistance to ground, find the output resistance of current source Q5 and of current source Q6 with R6 connected. Ignore base currents.

1 viewsvenkyelectrical Asked question 27 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.40 Design the circuit in Fig. 13.14 to generate a current I = 5 µA. Utilize transistors Q1 and Q2 having areas in a ratio of 1:4. Assume that Q3 and Q4 are matched and design for a 0.2-V drop across each of R3 and R4. Specify the values of R2, R3, and R4. Ignore base currents. 6.93 k; 40 k; 40 k

1 viewsvenkyelectrical Asked question 28 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.39 Design a Widlar current source shown in Fig. 13.14 so that all collector currents are 10 µA. Assume that VCC = 3 V, IS2 = 10−16, all other transistors have IS = 2·10−17, and all have high β. Find VBIAS1, VBIAS2, and the values of all resistors. The voltage drops across R3 and R4 should be 0.1 V.

1 viewsvenkyelectrical Asked question 29 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.38 For the folded-cascode circuit of Fig. 13.9, let the total capacitance to ground at each of the source nodes of Q3 and Q4 be denoted CP. Assuming that the incremental resistance between the drain of Q3 and ground is small, show that the pole that arises at the interface between the first and second stages has a frequency fP ≃ gm3/2πCP. Now, if this is the only nondominant pole, what is the largest value that CP can be (expressed as a fraction of CL) while a phase margin of 80° is achieved? Assume that all transistors are operated at the same bias current and overdrive voltage. 0.176CL

2 viewsvenkyelectrical Edited question 29 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.37 A particular design of the wide-swing current mirror of Fig. 13.13(b) utilizes devices in the 65-nm CMOS technology of Appendix K having W/L = 12, = 540 µA/V2, and Vt = 0.35 V. For IREF = 90 µA, what value of VBIAS is needed? Also give the voltages that you expect to appear at all nodes and specify the minimum voltage allowable at the output terminal. If VA is specified to be 1 V, what is the output resistance of the mirror?

1 viewsvenkyelectrical Asked question 31 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.36 For the circuit in Fig. 13.12, assume that all transistors are operating at equal overdrive voltages of 0.15-V magnitude and have |Vt| = 0.45 V and that VDD = VSS = 1V. Find (a) the range over which the NMOS input stage operates, (b) the range over which the PMOS input stage operates, (c) the range over which both operate (the overlap range), and (d) the input common-mode range. Assume that all current sources require a minimum voltage of |VOV| to operate properly. (a) −0.25 V ≤ VICM + 1.3 V; (b) −1.3 V ≤ VICM + 0.25 V; (c) −0.25 V ≤ VICM + 0.25 V; (d) −1.3 V ≤ VICM + 1.3 V

1 viewsvenkyelectrical Asked question 31 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

**13.35 This problem presents a very interesting addition to the folded-cascode op-amp circuit of Fig. 13.10, designed to deal with the situation during amplifier slewing. In particular, the additional circuitry does two things: It prevents Q1 and Q11 from going into the triode region, and it increases the current available to charge CL and thus increases the slew rate. The circuit is shown in Fig. P13.35 (with the current-mirror circuit omitted, for simplicity). Observe that three transistors are added: Q14, which is biased by a constant-current source (20 µA), establishes the dc currents in Q9 and Q10. Assume with respect to Q9 and Q10 that each has a W/L ratio 10 times that of Q14. The other two additional transistors are Q12 and Q13, which are diode connected and are normally cut off.

1 viewsvenkyelectrical Asked question 32 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D 13.34 Sketch the circuit that is complementary to that in Fig. 13.10, that is, one that uses an input p-channel differential pair.

1 viewsvenkyelectrical Asked question 33 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

D *13.33 Design the folded-cascode circuit of Fig. 13.10 to provide voltage gain of 80 dB and a unity-gain frequency of 20 MHz when CL = 10 pF. Design for IB = I, and operate all devices at the same |VOV|. Utilize transistors for which is specified to be 12 V. Find the required overdrive voltages and bias currents. What slew rate is achieved? Also, for the 0.25-µm CMOS technology of Appendix K in which and = 93 µA/V2, specify the required W/L of each of the 11 transistors used.

1 viewsvenkyelectrical Asked question 33 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.32 A folded-cascode amplifier is connected to its capacitive load CL through a series resistor RS as shown in Fig. P13.32. Find the frequency responses Vo/Vid and Vf/Vid. Show that Vf/Vid has a zero at fz = 1/2πRSCL. How may this technique be used in frequency compensation?

1 viewsvenkyelectrical Asked question 34 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

13.31 For a particular design of the folded-cascode op amp in Fig. 13.9, I < IB. What slew rate is obtained? I/CL

1 viewsvenkyelectrical Asked question 35 mins agoMicroelectronicsMicroelectronics by Sedra and Smith 8th edition Chapter 13

0 Votes 0 Ans

1 2 … 76 77