14.74 For a dc voltage of 1 V applied to the input of the circuit of Fig. 14.30(b), in which C1 is 1 pF, what charge is transferred for each cycle of the two-phase clock? For a 200-kHz clock, what is the average current drawn from the input source? For a feedback capacitance of 10 pF, what change would you expect in the output for each cycle of the clock? For an amplifier that saturates at ±1 V and the feedback capacitor initially discharged, how many clock cycles would it take to saturate the amplifier? What is the average slope of the staircase output voltage produced?
14.74 For a dc voltage of 1 V applied to the input of the circuit of Fig. 14.30(b), in which C1 is 1 pF, what charge is transferred for each cycle of the two-phase clock? For a 200-kHz clock, what is the average current drawn from the input source? For a feedback capacitance of 10 pF, what change would you expect in the output for each cycle of the clock? For an amplifier that saturates at ±1 V and the feedback capacitor initially discharged, how many clock cycles would it take to saturate the amplifier? What is the average slope of the staircase output voltage produced?
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