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venkyelectrical
venkyelectrical
Asked: January 16, 2022In: microelectronics

7.135 For the emitter follower in Fig. P7.135, the signal source is directly coupled to the transistor base. If the dc component of vsig is zero, find the dc emitter current. Assume β =100. Neglecting ro, find Rin, the voltage gain vo/vsig, the current gain io/ii, and the output resistance Rout.

7.135 For the emitter follower in Fig. P7.135, the signal source is directly coupled to the transistor base. If the dc component of vsig is zero, find the dc emitter current. Assume β =100. Neglecting ro, find Rin, the voltage ...

microelectronics by sedra and smith 8th edition chapter 7
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venkyelectrical
venkyelectrical
Asked: January 14, 2022In: microelectronics

7.33 Figure P7.33 shows a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). All capacitors behave as short circuits for signals and as open circuits for dc. (a) If the transistor has Vt = 1 V, and kn = 4 mA/V2, verify that the bias circuit establishes VGS = 1.5 V, ID = 0.5 mA, and VD = +7.0 V. That is, assume these values, and verify that they are consistent with the values of the circuit components and the device parameters.

7.33 Figure P7.33 shows a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown ...

microelectronics by sedra and smith 8th edition chapter 7
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venkyelectrical
venkyelectrical
Asked: January 8, 2022In: microelectronics

4.4 In each of the ideal-diode circuits shown in Fig. P4.4(a), (b), (c), (d), (e), (f), (g), (h), (i), (j), and (k), vI is a 1-kHz, 5-V peak sine wave. Sketch the waveform resulting at vO. What are its positive and negative peak values?

4.4 In each of the ideal-diode circuits shown in Fig. P4.4(a), (b), (c), (d), (e), (f), (g), (h), (i), (j), and (k), vI is a 1-kHz, 5-V peak sine wave. Sketch the waveform resulting at vO. What are its positive ...

microelectronics by sedra and smith 8th edition chapter 4
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venkyelectrical
venkyelectrical
Asked: January 16, 2022In: microelectronics

7.88 For the general amplifier circuit shown in Fig. P7.88 neglect the Early effect. (a) Find expressions for vc/vsig and ve/vsig. (b) If vsig is disconnected from node X, node X is grounded, and node Y is disconnected from ground and connected to vsig, find the new expression for vc/vsig.

7.88 For the general amplifier circuit shown in Fig. P7.88 neglect the Early effect. (a) Find expressions for vc/vsig and ve/vsig. (b) If vsig is disconnected from node X, node X is grounded, and node Y is disconnected from ground ...

microelectronics by sedra and smith 8th edition chapter 7
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venkyelectrical
venkyelectrical
Asked: January 4, 2022In: microelectronics

*2.68 (a) Find Ad and Acm for the difference amplifier circuit shown in Fig. P2.68. (b) If the op amp is specified to operate properly as long as the common-mode voltage at its positive and negative inputs falls in the range ±2.5 V, what is the corresponding limitation on the range of the input common-mode signal vIcm? (This is known as the common-mode range of the differential amplifier.) (c) The circuit is modified by connecting a 10- kΩ resistor between node A and ground, and another 10- kΩ resistor between node B and ground. What will now be the values of Ad, Acm, and the input common-mode range?

*2.68 (a) Find Ad and Acm for the difference amplifier circuit shown in Fig. P2.68. (b) If the op amp is specified to operate properly as long as the common-mode voltage at its positive and negative inputs falls in the range ...

microelectronics by sedra and smith 8th edition chapter 2
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venkyelectrical
venkyelectrical
Asked: February 12, 2022In: microelectronics

*9.23 Figure P9.23 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications:

*9.23 Figure P9.23 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The ...

microelectronics by sedra and smith 8th edition chapter 9
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venkyelectrical
venkyelectrical
Asked: January 16, 2022In: microelectronics

7.130 The amplifier of Fig. P7.130 consists of two identical common-emitter amplifiers connected in cascade. Observe that the input resistance of the second stage, Rin2, constitutes the load resistance of the first stage. (a) For VCC = 15 V, R1 = 100 kΩ, R2 = 47 kΩ, RE = 3.9 kΩ, RC = 6.8 kΩ, and β =100, determine the dc collector current and dc collector voltage of each transistor. (b) Draw the small-signal equivalent circuit of the entire amplifier and give the values of all its components. (c) Find Rin1 and vb1/vsig for Rsig = 5 kΩ. (d) Find Rin2 and vb2/vb1. (e) For RL =2 kΩ, find vo/vb2. (f) Find the overall voltage gain vo/vsig.

7.130 The amplifier of Fig. P7.130 consists of two identical common-emitter amplifiers connected in cascade. Observe that the input resistance of the second stage, Rin2, constitutes the load resistance of the first stage. (a) For VCC = 15 V, R1 = ...

microelectronics by sedra and smith 8th edition chapter 7
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