D 8.47 Design the CMOS amplifier of Fig. 8.16(a) utilizing the 0.13-µm process whose parameters are specified in Table K.1. The output voltage must be able to swing to within approximately 0.2 V of the power-supply rails (i.e., from 0.2 V to 1.1 V), and the voltage gain must be about 10 V/V. Design for a dc bias current of 50 µA, and use devices with the same channel length. If the channel length is an integer multiple of the minimum 0.13 µm, what channel length is needed and what W/L ratios are required? What gain is achieved? If it is required to raise the gain by a factor of 2, what channel length would be required, and by what factor does the total gate area of the circuit increase? VDD = 1.3 V.