D8.2 For the circuit of Fig. 8.4, let VDD = VSS = 1.5 V, Vtn = 0.6 V, Vtp = −0.6 V, all channel lengths = 1 µm, , and λ = 0. For IREF = 10 µA, find the widths of all transistors to obtain I2 = 60 µA, I3 = 20 µA, and I5 = 80 µA. The voltage at the drain of Q2 must be allowed to go down to within 0.2 V of the negative supply, and the voltage at the drain of Q5 must be allowed to go up to within 0.2 V of the positive supply.
W1 = 2.5 µm; W2 = 15 µm; W3 = 5 µm; W4 = 12.5 µm; W5 = 50 µm