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Home/compensator design using root locus

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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

TUTORIAL 12 – ROOT LOCUS DESIGN Objective • Integrate material from all previous lectures into a practical problem. • Practice for the Final exam. You are to design compensation for a servo aircraft pitch dynamics placed in a unity feedback system. The system is pictured below. Control Elevator servo Aircraft dynamics FIGURE 1: AIRCRAFT PITCH DYNAMICS You are provided transfer functions . (s) Elevator servo, 45 — — 10 ec(s) s + 10 0(s) 3 Aircraft dynamics,6,(s)— s2 + 3s + 4 1. Design a gain compensator that will produce closed loop system having damping ratio of 0.42 (desired poles approximately at -1.2±2.6i). Calculate the settling time for a step input, and the steady state error for a step input. 2. Design a new compensator that will eliminate the steady state error to a step input, while retaining % overshoot with similar step input settling time to gain compensation. Estimate the new settling time. 3. Design a new compensator that will decrease the step input settling time to one half of the value found for gain compensation, but with same % overshoot

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

Problem 4. Root-Locus Design (30 points) Consider the unity feedback system in the following figure G(s) — (s +2)(s + 4)(s + 6) K (a) Find K so that the system is operated with 10% overshoot. (b) Using root-locus method, design a lag compensator to improve the steady state error without appreciably changing the dominant pole location which will yield K,, = 20.

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

Question: G(S)H(S)=- S(S+)(+18) 1. Design A PD Controller Using Time-Domain Design Method Such That (1) K, = 50 And (2) Overshoot Is… G(s)H(s) — 1 s(s +6)(s +18) 1. Design a PD controller using time-domain design method such that (1) K, =50 and (2) overshoot is smallest.

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

Problem 1 (50 points) Consider a system with P(s) — u (s+1)(s+3) and controller K(s). You will design a compensator K(s) that results in a dosed loop system with w„ (natural frequency) = 4 r±, f(damping ratio) =1 using MATLAB (use rlOCUs function). controller E(s) R(s) K(s) plant P(s) C(s) a) In order to have a closed loop system with wn = 4 rasd , 3 = the closed loop poles should be located at s = —3 + jr7, —3 — jr7. Verify these pole locations using the natural frequency and damping ratio given using Pole-Plot (Hint: Check ‘4. Transientresponse’ lecture notes for Pole-Plot) (10points) b) If K(s)=K (K is a constant), can you find a value K that results in the closed loop poles at s = —3 ± j1/7? Explain using root locus. (10points) c) In order to move the closed loop poles to the desired location, you have decided to use lead compensator (K(s) = K, ss÷; (0 < z < p) so that we can move pull the root locus to the left. Choose z and p for this lead compensator by trying different values (It will take some time to find right values that satisfy the condition. There are many possible solutions). Using root locus in MATLAB to determine z and p for your lead compensator. Once you find the values, 1) plot a root locus using MATIAB and 2) mark the point on root locus where it passes through the desired pole location s = —3 ± NI using 'Data Tips' in MATLAB figure and 3) Record the 'Gain' value shown in the 'Data Tips' at this pole location (Hint: Make sure your two desired closed loop poles are dominant. In other words, the desired pole locations should be right to other poles. This allows us to treat our system as rd order system) (20 points). ** Note: You don't need to create lead compensator that makes the closed loop poles passes through right on the desired closed loop pole locations. If your root locus passes near those desired closed loop pole locations, that's enough. d) Using the magnitude condition (Hint: Check '11. Compensator Design' lecture note), find K, value of the compensator for the desired pole locations and compare this value with the gain you recorded in Part (c) (10points)

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

13. (25 points) An engineer generated the following root locus as part of their controller design process. The plant is an inverted pendulum with a torque input and the following transfer function: 1 G(s)= Js2 – mill a) What type of controller is being designed? b) For what range of gains is the system underdamped? c) What is the minimum gain that stabilizes the system? d) What is the control law that results from the gain in part c?

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

Question: Consider The System: G 0 ZOH G (S) = With Plant Specified As: 40000 Gp(S) S(S + 200) A) Design A Digital Compensator, Gp(2),… Consider the system: –t9— ‘Plc’? ZOH —No. 0 (S) With plant specified as: 40000 Gp(s) = s(s + 200) a) Design a digital compensator, Gc(z), using Root Locus such that the following specifications are satisfied: i) An Overshoot of at most 15% ii) A settling time of at most 0.02 seconds (using 2% criterion) b) Use Matlab to verify your design. Use a sampling time of T=1 ms for this task. Note that you must clearly document your design process/steps and clearly state and explain any assumptions that you make.

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

Question: Complex Engineering Design Problem R(S) Y(S) + Hoe 26 Figure 1 Task 1 Find Out The State-Space Representation And Transfer… Task 1 Find out the state-space representation and Transfer function of the system. Task 2 Use the transfer function of Task 1 and sketch root locus of the system. Task 3 Using root locus plot of Task 2 find the transient and steady state behavior of system for 3=0.3. Task 4 Design a suitable compensator for the above system that may reduce the settling time by a factor of 3 and the system has a percent overshoot of less than 4%.

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 16, 2022In: control systems engineering

Question: Question 2 (Controller Design Via Root Locus): Consider The Following Closed-Loop Control System Illustrated In Figure 2. T=0.2 S…

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 14, 2022In: control systems engineering

Exercise 9*: Lead-Lag design using Root Locus Recall the disc drive problem from Tutorials, where we demonstrated that the open-loop system can be written as (s)o Gc(s) Figure 8: Disc Drive System Block Diagram We will now try to design a lead-lag compensator with the requirements that • Overshoot < 10 • Ts < 75ms • era„,p(a)) 5 0.001 Do the following (you may use MATLAB at your leisure, but be sure to explain your logic for your design choices): a) Use MATLAB to draw the root locus when Ge = b) Use MATLAB to draw the region where the dominant dosed-loop poles must be to satisfy the transient requirements. Comment on your ability to achieve these requirements with a gain-only controller. c) Design a lead compensator(s) to meet the transient requirements (i.e. overshoot and settling time) d) Design a lag compensator to achieve the steady-state tracking requirement e) Use MATLAB to compute the resulting closed-loop poles and discuss second order dominance. Some Hints: • You may need to place more than one lead compensator for part c) • When assessing second order dominance of the dosed-loop system, be sure to cancel poles and zeros (i.e. use minrea:.)

compensator design using root locus
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venkyelectrical
venkyelectrical
Asked: April 14, 2022In: control systems engineering

Question : 1- Find transfer function (Vo/Vi) of the circuit Figure 1, then check your system is stable or not with unit feedback (with different methods: root locus, Bode plot, Nyquist ) ; inputs: step and ramp 2- Design lead-lag compensator to improve the settling time of 10% with respect to uncompensated system 3- Verify if the system with compensator is stable or not 4- In each step, calculate: gain margin and phase margin (Bode and Nyquist) 5- Add one pole in origin (1/s) to the system and check the impact of adding this pole to the system

compensator design using root locus
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Recent Comments

  1. venkyelectrical on Bonus Problem (10 points): In this circuit, the op amp is IDEAL. The op amp is NOT operating in the linear region. In this Circuit, V+=V_. The op amp output saturates at +12v. The output is always at saturation, either positive or negative. The output will “toggle” as Vin crosses a “threshold” voltage. Because of the positive feedback, the threshold voltage changes depending on the state of the output voltage. Find the lower and upper values of the threshold voltages to 5 places of precision.
  2. venkyelectrical on Problem #3 Operational Amplifiers (35 pts): The op amp is IDEAL and operating in the linear region. Find the voltage gain (Av) of the circuit. If Vin = -2, find io.
  3. venkyelectrical on Problem #2 Operational Amplifiers (35 pts): Op amp is ideal and operating in the linear region. Find the node voltages in the table.
  4. venkyelectrical on Problem #I Linear Amplifiers (40 pts) (SHOW ALL WORK) In the Problem, all resistor values are in ohms, voltages are volts and currents are amps. Amp “A” is voltage-to-current, Amps “B” and “C” are current-to-voltage. Use /1 = 0.01(V1), v2 = 100(/2) and V3 = 50(/3). Use Vin shown in the table. Find all the values listed in the table. Hint: Observe that R3, R4 and R5 are m parallel.
  5. venkyelectrical on 3. This problem is on the quantization and encoding. Answer to the following: Assume round-off rule for uniform quantization. We have 10 samples from the analog signal and their quantization error qε are found to be distributed as, qε =[0.33, 0.36, -0.38, 0.22, -0.4, 0.07, 0.4, -0.18, -0.25, 0.38] (a) Decide the suitable value of quantization step size ∆. Give reasoning for your answer (3) (b) We assume that qε are uniformly distributed with its probability density function f ∆ (∆) =1 /∆ for the interval [-∆/2, +∆/2]. Calculate the quantization noise power Pqε for the value of ∆ you found in part (a). (3) (c) Per the quantization noise power you calculated in part (b), calculate the signal power S [Watt] if output Signal to Q-zation noise power ratio SNRo = 30 dB. (3) (d) If we encode the quantizer output with binary code with length ‘n’(integer), decide the minimum code length ‘n’ based on the condition given in part (c) (1)

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