microelectronics by sedra and smith 8th edition chapter 13 Archives

Asked: February 23, 2022In: microelectronics

13.70 For the output stage in Fig. 13.30, find the current IREF that results in a quiescent current IQ = 0.6 mA. Assume that I = 12 µA, QN has eight times the area of Q10, and Q7 has four times the area of Q11. What is the minimum current in QN and QP? 10.6 A; minimum current is 0.3 mA

13.70 For the output stage in Fig. 13.30, find the current IREF that results in a quiescent current IQ = 0.6 mA. Assume that I = 12 µA, QN has eight times the area of Q10, and Q7 has four ...

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Asked: February 23, 2022In: microelectronics

13.69 It is required to derive the expression for vE in Eq. (13.89). Toward that end, note from the circuit in Fig. 13.30 that vE = vEB7 + vBEN and note that QN conducts a current iN and Q7 conducts a current iC7 given by Eq. (13.88).

13.69 It is required to derive the expression for vE in Eq. (13.89). Toward that end, note from the circuit in Fig. 13.30 that vE = vEB7 + vBEN and note that QN conducts a current iN and Q7 conducts ...

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Asked: February 23, 2022In: microelectronics

13.68 It is required to derive the expressions in Eqs. (13.87) and (13.88). Toward that end, first find vB7 in terms of vBEN and hence iN. Then find vB6 in terms of iP. For the latter purpose note that Q4 measures vEBP and develops a current i4 = (vEBP − vEB4)/R4). This current is supplied to the series connection of Q5 and R5 where R5 = R4. In the expression you obtain for vB6, use the relationship

13.68 It is required to derive the expressions in Eqs. (13.87) and (13.88). Toward that end, first find vB7 in terms of vBEN and hence iN. Then find vB6 in terms of iP. For the latter purpose note that Q4 ...

venkyelectrical

Asked: February 23, 2022In: microelectronics

13.67 The output stage in Fig. 13.28 operates at a quiescent current IQ of 0.6 mA. The maximum current iL that the stage can provide in either direction is 12 mA. The output stage is equipped with a feedback circuit that maintains a minimum current of IQ/2 in the inactive output transistor. Also, VCC = 3V. (a)What is the allowable range of vO? (b)For iL = 0, what is the output resistance of the op amp? (c)If the open-loop gain of the op amp is 100,000 V/V, find the closed-loop output resistance obtained when the op amp is connected in the unity-gain voltage follower configuration, with iL = 0. (d)If the op amp is sourcing a load current iL = 12 mA, find iP, iN, and the open-loop output resistance. (e)Repeat (d) for the case of the open-loop op amp sinking a load current of 12 mA. (a) 0.1 V ≤ v0 ≤ 2.9 V; (b) 20 k; (c) 0.2 ; (d) 12.3 mA; 0.3 mA; 1.6 k; (e) 12.3 mA; 0.3 mA; 2.4 k

13.67 The output stage in Fig. 13.28 operates at a quiescent current IQ of 0.6 mA. The maximum current iL that the stage can provide in either direction is 12 mA. The output stage is equipped with a feedback circuit ...

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Asked: February 23, 2022In: microelectronics

13.66 Figure P13.66 shows a circuit suitable for op-amp applications. For all transistors β = 100, VBE = 0.7 V, and ro = ∞. (a)For inputs grounded and output held at 0 V (by negative feedback) find the collector currents of all transistors. Neglect base currents. (b)Calculate the input resistance. (c)Calculate the gain of the amplifier with a load of 5 kΩ. (d)With load as in (c) calculate the value of the capacitor C required for a 3-dB frequency of 100 Hz.

13.66 Figure P13.66 shows a circuit suitable for op-amp applications. For all transistors β = 100, VBE = 0.7 V, and ro = ∞.

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Asked: February 23, 2022In: microelectronics

13.65 The VBE– multiplier circuit shown in Fig. P13.65 can replace the two series diode-connected transistors in Fig. 13.15 to establish the voltage drop needed to bias the output stage transistors. Design the circuit to provide a terminal voltage of 1.2 V. Base your design on half the current flowing through R1, and assume that IS =10−14 A and β = 200. What is the incremental resistance between the two terminals of the VBE– multiplier circuit?

13.65 The VBE– multiplier circuit shown in Fig. P13.65 can replace the two series diode-connected transistors in Fig. 13.15 to establish the voltage drop needed to bias the output stage transistors. Design the circuit to provide a terminal voltage of ...

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Asked: February 23, 2022In: microelectronics

13.64 Figure P13.64 shows the CMOS version of the circuit in Fig. P13.63. Find the relationship between I3 and I1 in terms of k1, k2, k3, and k4 of the four transistors, assuming the threshold voltages of all devices to be equal in magnitude. Note that k denotes μCoxW/L. In the event that k1 = k2 and k3 = k4 = 20k1, find the required value of I1 to yield a bias current in Q3 and Q4 of 0.2 mA.

13.64 Figure P13.64 shows the CMOS version of the circuit in Fig. P13.63. Find the relationship between I3 and I1 in terms of k1, k2, k3, and k4 of the four transistors, assuming the threshold voltages of all devices to ...

venkyelectrical

Asked: February 23, 2022In: microelectronics

13.63 For the circuit in Fig. P13.63, neglect base currents and use the exponential iC−vBE relationship to show that The figure shows a circuit utilizing n p n and p n p transistors. The n p n transistor Q subscript 2 has its emitter connected to ground. The base of Q subscript 2 is connected to the collector of Q subscript 2. The collector of Q subscript 2 is connected to the emitter of the n p n transistor Q subscript 1. The base of Q subscript 1 is connected to the collector of Q subscript 1. A current source I subscript 1 is connected between the collector of Q subscript 1 and the 15 volt supply voltage. The collector of Q subscript 1 is connected to the base of n p n transistor Q subscript 3. The collector of Q subscript 3 is connected to a 15 volts supply voltage. The emitter of Q subscript 3 is connected to the emitter of p n p transistor Q subscript 4. The base of Q subscript 4 is connected to ground. The collector of Q subscript 4 is connected to a negative 15 volt supply voltage. Figure P13.63 images Find I1 for the case in which IS3 = IS4 = 3 × 10−14 A, IS1 = IS2 = 10−14 A, and a bias current I3 = 150 µA is required. 50 A

13.63 For the circuit in Fig. P13.63, neglect base currents and use the exponential iC−vBE relationship to show that The figure shows a circuit utilizing n p n and p n p transistors. The n p n transistor Q subscript 2 ...

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Asked: February 23, 2022In: microelectronics

13.62 An alternative approach to that presented in Example 13.5 for determining the CMRR of the 741 input stage is investigated in this problem. Rather than performing the analysis on the closed loop shown in Fig. 13.27, we observe that the negative feedback increases the resistance at node Y by the amount of negative feedback. Thus, we can break the loop at Y and connect a resistance Rf = (1 + Aβ)Ro between the common-base connection of Q3−Q4 and ground. We can then determine the current i and Gmcm. Using the fact that the loop gain is approximately equal to βP (Exercise 13.17) show that this approach yields an identical result to that found in Example 13.5.

13.62 An alternative approach to that presented in Example 13.5 for determining the CMRR of the 741 input stage is investigated in this problem. Rather than performing the analysis on the closed loop shown in Fig. 13.27, we observe that ...

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Asked: February 23, 2022In: microelectronics

13.61 Consider the circuit of Fig. 13.27 modified to include resistors R in series with the emitters of each of Q5 and Q6. Assuming |VA| = 50 V, βp = 50, and IC6 = 20 A, what value of R provides Ro6 = 20 M Ω? How does this affect the CMRR calculated in Exercise 13.24?

13.61 Consider the circuit of Fig. 13.27 modified to include resistors R in series with the emitters of each of Q5 and Q6. Assuming |VA| = 50 V, βp = 50, and IC6 = 20 A, what value of R ...

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