16.35 Redo Exercise 16.5 using the following parameters from a 28-nm CMOS technology: VDD = 0.9 V, Vtn = −Vtp = 0.3 V, μn/μp = 1.5, and μnCox = 750 µA/V2. QN and QP have L = 28 nm and ...
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16.34 Repeat Example 16.3 for a CMOS inverter fabricated in a 0.13-µm process for which VDD = 1.3 V, Vtn = | Vtp | = 0.4 V, μn = 4μp, and μnCox = 500 µA/V2. In addition, QN and QP ...
16.33 Consider the CMOS inverter of Fig. 16.22 with QN and QP matched and with the input vI rising slowly from 0 to VDD. At what value of vI does the current flowing through QN and QP reach its peak? ...
16.32 There are situations in which QN and QP of the CMOS inverter are deliberately mismatched to realize a certain desired value for VM. Show that the value required of the parameter r of Eq. (16.40) is given by
16.31 A CMOS inverter for which kn = 5kp = 250 µA/V2 and Vt = 0.4 V is connected as shown in Fig. P16.31 to a sinusoidal signal source having a Thévenin equivalent voltage of 0.1-V peak amplitude and resistance ...
16.30 For a technology in which Vtn = 0.3VDD, show that the maximum current that the inverter can sink while its low-output level does not exceed 0.1 VDD is 0.065 Image. For VDD = 1.2V, Image = 500 µA/V2, find ...
16.29 Consider a CMOS inverter fabricated in a 0.25-µm CMOS process for which VDD = 2.5 V, Vtn = −Vtp = 0.5 V, and μnCox = 3.5 μpCox = 115µA/V2. In addition, QN and QP have L = 0.25µm and ...
16.28 Consider a CMOS inverter fabricated in a 65-nm CMOS process for which VDD = 1 V, Vtn = −Vtp = 0.35 V, and μnCox = 5.4μpCox = 540 µA/V2. In addition, QN and QP have L = 65 nmand ...
16.27 Derive an expression for VM of the pseudo-NMOS inverter shown in Fig. 16.21. You may assume that Vt = Vtn = |Vtp| and r ≡ kn/kp.
16.26 Consider a pseudo-NMOS inverter as shown in Fig. 16.21 and fabricated in a 65-nm CMOS technology for which VDD = 1.0 V, |Vt| = 0.35 V, kn/kp = 5.4, and kn = 540 µA/V2. (a)Find VOH. (b)Derive an equation for VOL ...