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Home/microelectronics by sedra and smith 8th edition chapter 16

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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.35 Redo Exercise 16.5 using the following parameters from a 28-nm CMOS technology: VDD = 0.9 V, Vtn = −Vtp = 0.3 V, μn/μp = 1.5, and μnCox = 750 µA/V2. QN and QP have L = 28 nm and (W/L)n = 2.0. (a) 84 nm (b) VOH = 0.9 V; VOL = 0 V; VIH = 0.49 V; VIL = NMH = NML = 0.41 V (c) rDSP = rDSN = 1.11 kΩ (d) r = 0.816; VM = 0.43 V

16.35 Redo Exercise 16.5 using the following parameters from a 28-nm CMOS technology: VDD = 0.9 V, Vtn = −Vtp = 0.3 V, μn/μp = 1.5, and μnCox = 750 µA/V2. QN and QP have L = 28 nm and ...

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.34 Repeat Example 16.3 for a CMOS inverter fabricated in a 0.13-µm process for which VDD = 1.3 V, Vtn = | Vtp | = 0.4 V, μn = 4μp, and μnCox = 500 µA/V2. In addition, QN and QP have L = 0.13 µm and (W/L)n = 1.5. For part (a) use VM = VDD/2 = 0.65 V.

16.34 Repeat Example 16.3 for a CMOS inverter fabricated in a 0.13-µm process for which VDD = 1.3 V, Vtn = | Vtp | = 0.4 V, μn = 4μp, and μnCox = 500 µA/V2. In addition, QN and QP ...

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.33 Consider the CMOS inverter of Fig. 16.22 with QN and QP matched and with the input vI rising slowly from 0 to VDD. At what value of vI does the current flowing through QN and QP reach its peak? Give an expression for the peak current, neglecting λn and λp. For Image = 540 µA/V2, (W/L)n = 1.5, VDD = 1.0 V, and Vtn = 0.35V, find the value of the peak current.

16.33 Consider the CMOS inverter of Fig. 16.22 with QN and QP matched and with the input vI rising slowly from 0 to VDD. At what value of vI does the current flowing through QN and QP reach its peak? ...

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.32 There are situations in which QN and QP of the CMOS inverter are deliberately mismatched to realize a certain desired value for VM. Show that the value required of the parameter r of Eq. (16.40) is given by images For a 65-nm process characterized by Vtn = −Vtp = 0.35V, VDD = 1.0V, and μn = 5.4μp, find the ratio Wp/Wn required to obtain VM = 0.6VDD. 135

16.32 There are situations in which QN and QP of the CMOS inverter are deliberately mismatched to realize a certain desired value for VM. Show that the value required of the parameter r of Eq. (16.40) is given by

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.31 A CMOS inverter for which kn = 5kp = 250 µA/V2 and Vt = 0.4 V is connected as shown in Fig. P16.31 to a sinusoidal signal source having a Thévenin equivalent voltage of 0.1-V peak amplitude and resistance of 100 kΩ. What signal voltage appears at node A with vI = +1.5 V? With vI = –1.5 V? 3.5 mV; 15.4 mV

16.31 A CMOS inverter for which kn = 5kp = 250 µA/V2 and Vt = 0.4 V is connected as shown in Fig. P16.31 to a sinusoidal signal source having a Thévenin equivalent voltage of 0.1-V peak amplitude and resistance ...

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.30 For a technology in which Vtn = 0.3VDD, show that the maximum current that the inverter can sink while its low-output level does not exceed 0.1 VDD is 0.065 Image. For VDD = 1.2V, Image = 500 µA/V2, find (W/L)n that permits this maximum current to be 0.1 mA.

16.30 For a technology in which Vtn = 0.3VDD, show that the maximum current that the inverter can sink while its low-output level does not exceed 0.1 VDD is 0.065 Image. For VDD = 1.2V, Image = 500 µA/V2, find ...

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.29 Consider a CMOS inverter fabricated in a 0.25-µm CMOS process for which VDD = 2.5 V, Vtn = −Vtp = 0.5 V, and μnCox = 3.5 μpCox = 115µA/V2. In addition, QN and QP have L = 0.25µm and (W/L)n = 1.5. Investigate the variation of VM with the ratio Wp/Wn. Specifically, calculate VM for (a) Wp = 3.5Wn (the matched case), (b) Wp = Wn (the minimum-size case); and (c) Wp = 2Wn (a compromise case). For cases (b) and (c), estimate the approximate reduction in NML and silicon area relative to the matched case (a).

16.29 Consider a CMOS inverter fabricated in a 0.25-µm CMOS process for which VDD = 2.5 V, Vtn = −Vtp = 0.5 V, and μnCox = 3.5 μpCox = 115µA/V2. In addition, QN and QP have L = 0.25µm and ...

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.28 Consider a CMOS inverter fabricated in a 65-nm CMOS process for which VDD = 1 V, Vtn = −Vtp = 0.35 V, and μnCox = 5.4μpCox = 540 µA/V2. In addition, QN and QP have L = 65 nmand (W/L)n = 1.5. (a)Find Wp that results in VM = VDD/2. What is the silicon area utilized by the inverter in this case? (b)For the matched case in (a), find the values of VOH, VOL, VIH, VIL, NML, and NMH. (c)For the matched case in (a), find the output resistance of the inverter in each of its two states. (a) Wp = 527 nm; area = 40,560 nm2 (b) VOH = 1 V; VOL = 0 V; VIH = 0.5375 V; VIL = 0.4625 V; NMH = NML = 0.4625V (c) rDSP = rDSN = 1.9Ω

16.28 Consider a CMOS inverter fabricated in a 65-nm CMOS process for which VDD = 1 V, Vtn = −Vtp = 0.35 V, and μnCox = 5.4μpCox = 540 µA/V2. In addition, QN and QP have L = 65 nmand ...

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.27 Derive an expression for VM of the pseudo-NMOS inverter shown in Fig. 16.21. You may assume that Vt = Vtn = |Vtp| and r ≡ kn/kp.

16.27 Derive an expression for VM of the pseudo-NMOS inverter shown in Fig. 16.21. You may assume that Vt = Vtn = |Vtp| and r ≡ kn/kp.

microelectronics by sedra and smith 8th edition chapter 16
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venkyelectrical
venkyelectrical
Asked: March 19, 2022In: microelectronics

16.26 Consider a pseudo-NMOS inverter as shown in Fig. 16.21 and fabricated in a 65-nm CMOS technology for which VDD = 1.0 V, |Vt| = 0.35 V, kn/kp = 5.4, and kn = 540 µA/V2. (a)Find VOH. (b)Derive an equation for VOL that is a function of VDD, Vt, and kn/kp. (c)Evaluate the equation using the process parameters in the problem statement.

16.26 Consider a pseudo-NMOS inverter as shown in Fig. 16.21 and fabricated in a 65-nm CMOS technology for which VDD = 1.0 V, |Vt| = 0.35 V, kn/kp = 5.4, and kn = 540 µA/V2. (a)Find VOH. (b)Derive an equation for VOL ...

microelectronics by sedra and smith 8th edition chapter 16
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Recent Comments

  1. venkyelectrical on Bonus Problem (10 points): In this circuit, the op amp is IDEAL. The op amp is NOT operating in the linear region. In this Circuit, V+=V_. The op amp output saturates at +12v. The output is always at saturation, either positive or negative. The output will “toggle” as Vin crosses a “threshold” voltage. Because of the positive feedback, the threshold voltage changes depending on the state of the output voltage. Find the lower and upper values of the threshold voltages to 5 places of precision.
  2. venkyelectrical on Problem #3 Operational Amplifiers (35 pts): The op amp is IDEAL and operating in the linear region. Find the voltage gain (Av) of the circuit. If Vin = -2, find io.
  3. venkyelectrical on Problem #2 Operational Amplifiers (35 pts): Op amp is ideal and operating in the linear region. Find the node voltages in the table.
  4. venkyelectrical on Problem #I Linear Amplifiers (40 pts) (SHOW ALL WORK) In the Problem, all resistor values are in ohms, voltages are volts and currents are amps. Amp “A” is voltage-to-current, Amps “B” and “C” are current-to-voltage. Use /1 = 0.01(V1), v2 = 100(/2) and V3 = 50(/3). Use Vin shown in the table. Find all the values listed in the table. Hint: Observe that R3, R4 and R5 are m parallel.
  5. venkyelectrical on 3. This problem is on the quantization and encoding. Answer to the following: Assume round-off rule for uniform quantization. We have 10 samples from the analog signal and their quantization error qε are found to be distributed as, qε =[0.33, 0.36, -0.38, 0.22, -0.4, 0.07, 0.4, -0.18, -0.25, 0.38] (a) Decide the suitable value of quantization step size ∆. Give reasoning for your answer (3) (b) We assume that qε are uniformly distributed with its probability density function f ∆ (∆) =1 /∆ for the interval [-∆/2, +∆/2]. Calculate the quantization noise power Pqε for the value of ∆ you found in part (a). (3) (c) Per the quantization noise power you calculated in part (b), calculate the signal power S [Watt] if output Signal to Q-zation noise power ratio SNRo = 30 dB. (3) (d) If we encode the quantizer output with binary code with length ‘n’(integer), decide the minimum code length ‘n’ based on the condition given in part (c) (1)

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