microelectronics by sedra and smith 8th edition chapter 17 Archives

Asked: March 19, 2022In: microelectronics

17.35 An NMOS transistor with kn = 0.4 mA/V2 and a nominal Vtn of 0.4 V is to operate in saturation at ID = 0.2 mA. (a)If Vtn can vary by as much as ±10%, what is the expected range of ID obtained? (b)If the transistor is used to discharge a 100-fF load capacitance, what is the expected variation in delay time, assuming that the output voltage is to change by 0.1 V? (a) 0.184 to 0.216 mA (b) 46.3 to 54.3 ps

17.35 An NMOS transistor with kn = 0.4 mA/V2 and a nominal Vtn of 0.4 V is to operate in saturation at ID = 0.2 mA. (a)If Vtn can vary by as much as ±10%, what is the expected range of ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.34 Consider the scaling from a 0.13-µm process to a 65-nm process. (a)Assuming VDD and Vt are scaled by the same factor as the device dimensions (S = 2), find the factor by which tP, the maximum operating speed, Pdyn, power density, and PDP decrease (or increase)? (b)Repeat (a) for the situation in which VDD and Vt remain unchanged.

17.34 Consider the scaling from a 0.13-µm process to a 65-nm process. (a)Assuming VDD and Vt are scaled by the same factor as the device dimensions (S = 2), find the factor by which tP, the maximum operating speed, Pdyn, power ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.33 In this problem, we estimate the CMOS inverter power dissipation resulting from the current pulse that flows in QN and QP when the input pulse has finite rise and fall times. Refer to Fig. 17.13 and let Vtn = −Vtp = 0.4 V, VDD = 1.2 V, and kn = kp = 500 µA/V2. Let the input rising and falling edges be linear ramps with the 0-to-VDD and VDD -to-0 transitions taking 1 ns each. Find Ipeak. To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from Vt to VDD − Vt, and the height equal to Ipeak. Also, determine the power dissipation that results when the inverter is switched at 100 MHz.

17.33 In this problem, we estimate the CMOS inverter power dissipation resulting from the current pulse that flows in QN and QP when the input pulse has finite rise and fall times. Refer to Fig. 17.13 and let Vtn = ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.32 A logic-circuit family with zero static power dissipation normally operates at VDD = 1.8 V. To reduce its dynamic power dissipation, operation at 1.2 V is considered. It is found, however, that the currents available to charge and discharge load capacitances also decrease. If current is (a) proportional to VDD or (b) proportional to images what reductions in maximum operating frequency do you expect in each case? What fractional change in delay–power product do you expect in each case?

17.32 A logic-circuit family with zero static power dissipation normally operates at VDD = 1.8 V. To reduce its dynamic power dissipation, operation at 1.2 V is considered. It is found, however, that the currents available to charge and discharge ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.31 We wish to investigate the design of the inverter shown in Fig. 16.17(a). In particular, we wish to determine the value for R. Selection of a suitable value for R is determined by two considerations: propagation delay and power dissipation. (a)Show that if vI changes instantaneously from high to low and assuming that the switch opens instantaneously, the output voltage obtained across a load capacitance C will be images where τ1 = CR. Hence show that the time required for vO(t) to reach the 50% point, images, is images (b)Following a steady state, if vI goes high and assuming that the switch closes immediately and has the equivalent circuit in Fig. 16.17(c), show that the output falls exponentially according to images where images Hence show that the time for vO(t) to reach the 50% point is images (c)Use the results of (a) and (b) to obtain the inverter propagation delay, defined as the average of tPLH and tPHL as images (d)Show that for an inverter that spends half the time in the logic-0 state and half the time in the logic-1 state, the average static power dissipation is images (e)Now that the trade-offs in selecting R should be clear, show that, for VDD = 1.8 V and C = 2 pF, to obtain a propagation delay no greater than 1.4 ns and a power dissipation no greater than 2 mW, R should be in a specific range. Find that range and select an appropriate value for R. Then determine the resulting values of tP and P.

17.31 We wish to investigate the design of the inverter shown in Fig. 16.17(a). In particular, we wish to determine the value for R. Selection of a suitable value for R is determined by two considerations: propagation delay and power ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.30 A particular logic gate has tPLH and tPHL of 1.3 ns and 1.2 ns, respectively, and dissipates 0.1 mW with output low and 0.2 mW with output high. Calculate the corresponding delay–power product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation). 0.188 pJ

17.30 A particular logic gate has tPLH and tPHL of 1.3 ns and 1.2 ns, respectively, and dissipates 0.1 mW with output low and 0.2 mW with output high. Calculate the corresponding delay–power product (under the assumption of a 50% ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.29 A collection of logic gates for which the static power dissipation is zero, and the dynamic power dissipation is 10 mW is operating at 1 GHz with a 1.2-V supply. By what fraction could the power dissipation be reduced if operation at 1.0 V were possible? If the frequency of operation is reduced by the same factor as the supply voltage (i.e., 1.0/1.2), what additional power can be saved?

17.29 A collection of logic gates for which the static power dissipation is zero, and the dynamic power dissipation is 10 mW is operating at 1 GHz with a 1.2-V supply. By what fraction could the power dissipation be reduced ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.28 In a particular logic-circuit technology, operating with a 1.2-V supply, the basic inverter draws (from the supply) a current of 15 µA in one state and 0 µA in the other. When the inverter is switched at the rate of 250 MHz, the average supply current becomes 60 µA. Estimate the equivalent capacitance at the output node of the inverter. 0.175 pF

17.28 In a particular logic-circuit technology, operating with a 1.2-V supply, the basic inverter draws (from the supply) a current of 15 µA in one state and 0 µA in the other. When the inverter is switched at the rate ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.27 Consider a standard CMOS logic inverter. Let VDD = 1 V, and let a 5-fF capacitance be connected between the output node and ground. Assume there are no other capacitances. If the inverter is switched at the rate of 2.5 GHz, determine the dynamic power dissipation. What is the average current drawn from the dc power supply?

17.27 Consider a standard CMOS logic inverter. Let VDD = 1 V, and let a 5-fF capacitance be connected between the output node and ground. Assume there are no other capacitances. If the inverter is switched at the rate of ...

venkyelectrical

Asked: March 19, 2022In: microelectronics

17.26 An IC inverter fabricated in a 65-nm CMOS process is found to have a load capacitance of 3 fF. If the inverter is operated from a 1.2-V power supply, find the energy needed to charge and discharge the load capacitance. If the IC chip has 5 million of these inverters operating at an average switching frequency of 2.5 GHz, what is the power dissipated in the chip? What is the average current drawn from the power supply? 4.32 fJ; 54 W; 45 A

17.26 An IC inverter fabricated in a 65-nm CMOS process is found to have a load capacitance of 3 fF. If the inverter is operated from a 1.2-V power supply, find the energy needed to charge and discharge the load ...

10. a. Xis a Gaussian random variable with EMI = ...

1.1 For the signal-source representations shown in Figs. 1.1(a) and ...

1.2 A signal source has an open-circuit voltage of 10 ...

hwmadeeasy

mycala

https://lokt.page.link/Gidr <- PRACTICE BLACKJACK

Sign Up

Sign In

Forgot Password

electricalstudent.com Latest Questions