17.35 An NMOS transistor with kn = 0.4 mA/V2 and a nominal Vtn of 0.4 V is to operate in saturation at ID = 0.2 mA. (a)If Vtn can vary by as much as ±10%, what is the expected range of ...

## electricalstudent Latest Questions

17.34 Consider the scaling from a 0.13-µm process to a 65-nm process. (a)Assuming VDD and Vt are scaled by the same factor as the device dimensions (S = 2), find the factor by which tP, the maximum operating speed, Pdyn, power ...

17.33 In this problem, we estimate the CMOS inverter power dissipation resulting from the current pulse that flows in QN and QP when the input pulse has finite rise and fall times. Refer to Fig. 17.13 and let Vtn = ...

17.32 A logic-circuit family with zero static power dissipation normally operates at VDD = 1.8 V. To reduce its dynamic power dissipation, operation at 1.2 V is considered. It is found, however, that the currents available to charge and discharge ...

17.31 We wish to investigate the design of the inverter shown in Fig. 16.17(a). In particular, we wish to determine the value for R. Selection of a suitable value for R is determined by two considerations: propagation delay and power ...

17.30 A particular logic gate has tPLH and tPHL of 1.3 ns and 1.2 ns, respectively, and dissipates 0.1 mW with output low and 0.2 mW with output high. Calculate the corresponding delay–power product (under the assumption of a 50% ...

17.29 A collection of logic gates for which the static power dissipation is zero, and the dynamic power dissipation is 10 mW is operating at 1 GHz with a 1.2-V supply. By what fraction could the power dissipation be reduced ...

17.28 In a particular logic-circuit technology, operating with a 1.2-V supply, the basic inverter draws (from the supply) a current of 15 µA in one state and 0 µA in the other. When the inverter is switched at the rate ...

17.27 Consider a standard CMOS logic inverter. Let VDD = 1 V, and let a 5-fF capacitance be connected between the output node and ground. Assume there are no other capacitances. If the inverter is switched at the rate of ...

17.26 An IC inverter fabricated in a 65-nm CMOS process is found to have a load capacitance of 3 fF. If the inverter is operated from a 1.2-V power supply, find the energy needed to charge and discharge the load ...