18.45 Consider the use of the tree column decoder shown in Fig. 18.37 for application with a square 1-Mbit array. How many address bits are involved? How many levels of pass gates are used? How many pass transistors are there ...

## electricalstudent Latest Questions

18.44 For the column decoder shown in Fig. 18.37, how many column-address bits are needed in a 1-Mbit-square array? How many NMOS pass transistors are needed in the multiplexer? How many NMOS transistors are needed in the NOR decoder? How ...

18.43 Consider a 1024-row NOR decoder. To how many address bits does this correspond? How many output lines does the decoder have? How many input lines does the NOR array require? How many NMOS and PMOS transistors does such a ...

18.42 (a) For the sense amplifier of Fig. 18.34, show that the time required for the bit lines to reach 0.9VDD and 0.1VDD is given by td = (CB/Gm)ln(0.8VDD/ΔV), where ΔV is the initial difference voltage between the two bit ...

18.41 A particular version of the regenerative sense amplifier of Fig. 18.34 in a 0.13-µm technology uses transistors for which |Vt| = 0.4 V, images = 500 µA/V2, VDD = 1.2 V, with (W/L)n = 0.26 µm/0.13 µmand(W/L)p = 1.04 ...

18.40 Consider the operation of the differential sense amplifier of Fig. 18.34 following the rise of the sense control signal ϕs. Assume that a balanced differential signal of 0.1 V is established between the bit lines, each of which has ...

18.39 Design the one-shot circuit of Fig. 18.33 to provide an output pulse of 0.8-ns width. If the inverters available have tP = 200-ps delay, how many inverters do you need for the delay circuit?

18.38 A ring-of-nine oscillator is found to operate at 250 MHz. Find the propagation delay of the inverter. If the supply voltage is reduced by 20%, at what frequency do you expect the circuit to oscillate? 222 ps; 200 MHz

18.37 Consider a ring oscillator consisting of five inverters, each having tPLH = 300 ps and tPHL = 200 ps. Sketch one of the output waveforms, and specify its frequency and the percentage of the cycle during which the output ...

18.36 For a DRAM cell utilizing a capacitance of 25 fF, refresh is required within 12 ms. If a signal loss on the capacitor of 0.2 V can be tolerated, what is the largest acceptable leakage current present at the ...