microelectronics by sedra and smith 8th edition chapter 8 Archives

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venkyelectrical

Asked: January 19, 2022In: microelectronics

D 8.94 If the pnp transistor in the circuit of Fig. P8.94 is characterized by its exponential relationship with a scale current IS, show that the dc current I is determined by IR = VT ln(I/IS). Assume Q1 and Q2 to be matched and Q3, Q4, and Q5 to be matched. Find the value of R that yields a current I = 100 µA. For the BJT, VEB = 0.7 V at IE = 1mA

D 8.94 If the pnp transistor in the circuit of Fig. P8.94 is characterized by its exponential relationship with a scale current IS, show that the dc current I is determined by IR = VT ln(I/IS). Assume Q1 and Q2 ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

D 8.93 (a) For the circuit in Fig. P8.93, assume BJTs with high β and vBE = 0.7 V at 1 mA. Find the value of R that will result in IO = 10 µA. (b) For the design in (a), find Ro assuming β = 100 and VA = 50 V.

D 8.93 (a) For the circuit in Fig. P8.93, assume BJTs with high β and vBE = 0.7 V at 1 mA. Find the value of R that will result in IO = 10 µA. (b) For the design in (a), ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

D 8.92 (a) Utilizing a reference current of 200 µA, design a Widlar current source to provide an output current of 20 µA. Assume β to be high. (b) If β = 200 and VA = 50 V, find the value of the output resistance, and find the change in output current corresponding to a 5-V change in output voltage.

D 8.92 (a) Utilizing a reference current of 200 µA, design a Widlar current source to provide an output current of 20 µA. Assume β to be high. (b) If β = 200 and VA = 50 V, find the value ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

8.91 Using the idea employed in the modified Wilson MOS mirror in Fig. 8.38(c), modify the Wilson BJT mirror of Fig. 8.37(a) to eliminate the systematic error resulting from the difference in VCE of Q1 and Q2.

8.91 Using the idea employed in the modified Wilson MOS mirror in Fig. 8.38(c), modify the Wilson BJT mirror of Fig. 8.37(a) to eliminate the systematic error resulting from the difference in VCE of Q1 and Q2.

venkyelectrical

Asked: January 19, 2022In: microelectronics

8.90 Consider the Wilson MOS mirror of Fig. 8.88(a) for the case of all transistors identical, with W/L = 10, μnCox = 400 µA/V2, Vtn = 0.5 V, and VA = 18 V. The mirror is fed with IREF = 180 µA. (a) Obtain an estimate of VOV and VGS at which the three transistors are operating, by neglecting the Early effect. (b) Noting that Q1 and Q2 are operating at different VDS, obtain an approximate value for the difference in their currents and hence determine IO. (c) To eliminate the systematic error between IO and IREF caused by the difference in VDS between Q1 and Q2, a diode-connected transistor Q4 can be added to the circuit as shown in Fig. 8.38(c). What do you estimate IO to be now? (d) What is the minimum allowable voltage at the output node of the mirror? (e) Convince yourself that Q4 will have no effect on the output resistance of the mirror. Find Ro. (f) What is the change in IO (both absolute value and percentage) that results from ΔVO = 1 V?

8.90 Consider the Wilson MOS mirror of Fig. 8.88(a) for the case of all transistors identical, with W/L = 10, μnCox = 400 µA/V2, Vtn = 0.5 V, and VA = 18 V. The mirror is fed with IREF = ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

8.89 Show that the incremental input resistance (seen by IREF) for the Wilson MOS mirror of Fig. 8.38(a) is 2/gm. Assume that all three transistors are identical and neglect the Early effect. Also, assume a signal ground at the output. (Hint)

8.89 Show that the incremental input resistance (seen by IREF) for the Wilson MOS mirror of Fig. 8.38(a) is 2/gm. Assume that all three transistors are identical and neglect the Early effect. Also, assume a signal ground at the output. ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

8.88 The Wilson MOS mirror in Fig. 8.38(a) is fabricated in the 0.13-µm CMOS process specified in Table K.1. All three transistors are identical with channel length L = 4Lmin and W/L = 16. For IREF = 100 µA, find the voltage at the gates of Q1 and Q2, and the voltage at the gate of Q3. What is the minimum voltage required at the drain of Q3 for proper operation of the mirror? Find the output resistance Ro. 0.56 V; 1.12 V; 0.72 V

8.88 The Wilson MOS mirror in Fig. 8.38(a) is fabricated in the 0.13-µm CMOS process specified in Table K.1. All three transistors are identical with channel length L = 4Lmin and W/L = 16. For IREF = 100 µA, find ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

*8.87 For the Wilson current mirror of Fig. 8.37(a), show that the incremental input resistance seen by IREF is approximately 2VT/IREF. (Neglect the Early effect in this derivation and assume a signal ground at the output.) Evaluate Rin for IREF = 0.2 mA.

*8.87 For the Wilson current mirror of Fig. 8.37(a), show that the incremental input resistance seen by IREF is approximately 2VT/IREF. (Neglect the Early effect in this derivation and assume a signal ground at the output.) Evaluate Rin for IREF ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

D 8.86 Use the pnp version of the Wilson current mirror to design a 0.1-mA current source. The current source is required to operate with the voltage at its output terminal as low as –1.5 V. If the power supplies available are ±1.5 V, what is the highest voltage possible at the output terminal?

D 8.86 Use the pnp version of the Wilson current mirror to design a 0.1-mA current source. The current source is required to operate with the voltage at its output terminal as low as –1.5 V. If the power supplies ...

venkyelectrical

Asked: January 19, 2022In: microelectronics

D 8.85 (a) The circuit in Fig. P8.85 is a modified version of the Wilson current mirror. Here the output transistor is “split” into two matched transistors, Q3 and Q4. Find IO1 and IO2 in terms of IREF. Assume all transistors to be matched with current gain β.

D 8.85 (a) The circuit in Fig. P8.85 is a modified version of the Wilson current mirror. Here the output transistor is “split” into two matched transistors, Q3 and Q4. Find IO1 and IO2 in terms of IREF. Assume all ...

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D 8.93 (a) For the circuit in Fig. P8.93, assume BJTs with high β and vBE = 0.7 V at 1 mA. Find the value of R that will result in IO = 10 µA. (b) For the design in (a), find Ro assuming β = 100 and VA = 50 V.

8.91 Using the idea employed in the modified Wilson MOS mirror in Fig. 8.38(c), modify the Wilson BJT mirror of Fig. 8.37(a) to eliminate the systematic error resulting from the difference in VCE of Q1 and Q2.

8.89 Show that the incremental input resistance (seen by IREF) for the Wilson MOS mirror of Fig. 8.38(a) is 2/gm. Assume that all three transistors are identical and neglect the Early effect. Also, assume a signal ground at the output. (Hint)

*8.87 For the Wilson current mirror of Fig. 8.37(a), show that the incremental input resistance seen by IREF is approximately 2VT/IREF. (Neglect the Early effect in this derivation and assume a signal ground at the output.) Evaluate Rin for IREF = 0.2 mA.

D 8.86 Use the pnp version of the Wilson current mirror to design a 0.1-mA current source. The current source is required to operate with the voltage at its output terminal as low as –1.5 V. If the power supplies available are ±1.5 V, what is the highest voltage possible at the output terminal?

D 8.85 (a) The circuit in Fig. P8.85 is a modified version of the Wilson current mirror. Here the output transistor is “split” into two matched transistors, Q3 and Q4. Find IO1 and IO2 in terms of IREF. Assume all transistors to be matched with current gain β.

10. a. Xis a Gaussian random variable with EMI = ...

1.1 For the signal-source representations shown in Figs. 1.1(a) and ...

1.2 A signal source has an open-circuit voltage of 10 ...

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