Lost your password? Please enter your email address. You will receive a link and will create a new password via email.
Please briefly explain why you feel this question should be reported.
Please briefly explain why you feel this answer should be reported.
Please briefly explain why you feel this user should be reported.
9.116 The MOS differential amplifier shown in Fig. P9.116 utilizes three current mirrors for signal transmission: Q4−Q6 has a transmission factor of 2 [i.e., (W/L)6/(W/L)4 = 2], Q3−Q5 has a transmission factor of 1, and Q7−Q8 has a transmission factor ...
9.115 Figure P9.115 shows a three-stage amplifier in which the stages are directly coupled. The amplifier, however, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the ...
9.114 (a) If, in the multistage amplifier of Fig. 9.38, the resistor R5 is replaced by a constant-current source images 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become? ...
D 9.113 Consider the circuit of Fig. 9.38 and its output resistance. Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor ...
9.112 In the multistage amplifier of Fig. 9.38, emitter resistors are to be introduced: 100 Ω in the emitter lead of each of the first-stage transistors and 25 Ω for each of the second-stage transistors. What is the effect on ...
9.110 Figure P9.110 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig. 9.37. Here, the input differential pair Q1–Q2 is loaded in a current mirror formed by Q3 and Q4. The second stage is formed by ...
9.109 The two-stage op amp in Figure P9.105 is fabricated in a 65-nm technology having images = 540 µA/V2 and Vtn = −Vtp = 0.35 V. The amplifier is operated with VDD = +1.2 V and VSS = 0 V. (a)Perform ...
9.108 Consider the input stage of the CMOS op amp in Fig. 9.37 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q3 and Q4 have a ...
9.107 Consider the amplifier of Fig. 9.37, whose parameters are specified in Example 9.6. If a manufacturing error results in the W/L ratio of Q7 being 24/0.4, find the current that Q7 will now conduct. Thus find the systematic offset ...
D *9.106 In a particular design of the CMOS op amp of Fig. 9.37 the designer wishes to investigate the effects of increasing the W/L ratio of both Q1 and Q2 by a factor of 4. Assuming that all other ...