microelectronics by sedra and smith 8th edition chapter 9 Archives

Asked: February 13, 2022In: microelectronics

9.116 The MOS differential amplifier shown in Fig. P9.116 utilizes three current mirrors for signal transmission: Q4−Q6 has a transmission factor of 2 [i.e., (W/L)6/(W/L)4 = 2], Q3−Q5 has a transmission factor of 1, and Q7−Q8 has a transmission factor of 2. All transistors are sized to operate at the same overdrive voltage, |VOV|. All transistors have the same Early voltage |VA|.

9.116 The MOS differential amplifier shown in Fig. P9.116 utilizes three current mirrors for signal transmission: Q4−Q6 has a transmission factor of 2 [i.e., (W/L)6/(W/L)4 = 2], Q3−Q5 has a transmission factor of 1, and Q7−Q8 has a transmission factor ...

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Asked: February 13, 2022In: microelectronics

9.115 Figure P9.115 shows a three-stage amplifier in which the stages are directly coupled. The amplifier, however, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest.

9.115 Figure P9.115 shows a three-stage amplifier in which the stages are directly coupled. The amplifier, however, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the ...

venkyelectrical

Asked: February 13, 2022In: microelectronics

9.114 (a) If, in the multistage amplifier of Fig. 9.38, the resistor R5 is replaced by a constant-current source images 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become? Assume that the output resistance of the current source is very high. Use the results of Example 9.8. (b) With the modification suggested in (a), what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 Ω to ground? The original amplifier (before modification) has an output resistance of 152 Ω and a voltage gain of 8513 V/V. What is its gain when loaded by 100 Ω? Comment. Use β = 100.

9.114 (a) If, in the multistage amplifier of Fig. 9.38, the resistor R5 is replaced by a constant-current source images 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become? ...

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Asked: February 13, 2022In: microelectronics

D 9.113 Consider the circuit of Fig. 9.38 and its output resistance. Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor of 2? What will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to approximately its prior value? R5. 7.37 kΩ; reduced by a factor of 2; reduce R4 to 1.085 kΩ.

D 9.113 Consider the circuit of Fig. 9.38 and its output resistance. Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor ...

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Asked: February 13, 2022In: microelectronics

9.112 In the multistage amplifier of Fig. 9.38, emitter resistors are to be introduced: 100 Ω in the emitter lead of each of the first-stage transistors and 25 Ω for each of the second-stage transistors. What is the effect on input resistance, the voltage gain of the first stage, and the overall voltage gain? Use the bias values found in Example 9.7.

9.112 In the multistage amplifier of Fig. 9.38, emitter resistors are to be introduced: 100 Ω in the emitter lead of each of the first-stage transistors and 25 Ω for each of the second-stage transistors. What is the effect on ...

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Asked: February 13, 2022In: microelectronics

9.110 Figure P9.110 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig. 9.37. Here, the input differential pair Q1–Q2 is loaded in a current mirror formed by Q3 and Q4. The second stage is formed by the current-source-loaded common-emitter transistor Q5. Unlike the CMOS circuit, here there is an output stage formed by the emitter follower Q6. The function of capacitor CC will be explained later, in Chapter 11. All transistors have β = 100, |VBE| = 0.7 V, and ro = ∞.

9.110 Figure P9.110 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig. 9.37. Here, the input differential pair Q1–Q2 is loaded in a current mirror formed by Q3 and Q4. The second stage is formed by ...

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Asked: February 13, 2022In: microelectronics

9.109 The two-stage op amp in Figure P9.105 is fabricated in a 65-nm technology having images = 540 µA/V2 and Vtn = −Vtp = 0.35 V. The amplifier is operated with VDD = +1.2 V and VSS = 0 V. (a)Perform a dc design that will cause each of Q1, Q2, Q3, and Q4 to conduct a drain current of 200 µA and each of Q6 and Q7 to conduct a current of 400 µA. Design so that all transistors operate at 0.15-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present all results in a table. (b)Find the input common-mode range. (c)Find the allowable range of the output voltage. (d)With vA = vid/2 and vB = −vid/2, find the voltage gain vo/vid. Assume an Early voltage of 2.4 V.

9.109 The two-stage op amp in Figure P9.105 is fabricated in a 65-nm technology having images = 540 µA/V2 and Vtn = −Vtp = 0.35 V. The amplifier is operated with VDD = +1.2 V and VSS = 0 V. (a)Perform ...

venkyelectrical

Asked: February 13, 2022In: microelectronics

9.108 Consider the input stage of the CMOS op amp in Fig. 9.37 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q3 and Q4 have a mismatch ∆Vt. Show that a current gm3∆Vt appears at the output of the first stage. What is the corresponding input offset voltage?

9.108 Consider the input stage of the CMOS op amp in Fig. 9.37 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q3 and Q4 have a ...

venkyelectrical

Asked: February 13, 2022In: microelectronics

9.107 Consider the amplifier of Fig. 9.37, whose parameters are specified in Example 9.6. If a manufacturing error results in the W/L ratio of Q7 being 24/0.4, find the current that Q7 will now conduct. Thus find the systematic offset voltage that will appear at the output. (Use the results of Example 9.6.) Assuming that the open-loop gain will remain approximately unchanged from the value found in Example 9.6, find the corresponding value of input offset voltage, VOS. 120 μA; 455 mV; 0.73 mV

9.107 Consider the amplifier of Fig. 9.37, whose parameters are specified in Example 9.6. If a manufacturing error results in the W/L ratio of Q7 being 24/0.4, find the current that Q7 will now conduct. Thus find the systematic offset ...

venkyelectrical

Asked: February 13, 2022In: microelectronics

D *9.106 In a particular design of the CMOS op amp of Fig. 9.37 the designer wishes to investigate the effects of increasing the W/L ratio of both Q1 and Q2 by a factor of 4. Assuming that all other parameters are kept unchanged, refer to Example 9.6 to help you answer the following questions: (a)What change results in |VOV| and in gm of Q1 and Q2? (b)What change results in the voltage gain of the input stage? In the overall voltage gain? (c)What is the effect on the input offset voltages? (You might wish to refer to Section 9.4). – |Vov| is reduced by a factor of 2 and gm increases by a factor of 20; (b) Both increase by a factor of 20; (c) increases by a factor 2 (except for Vos due to ΔVt).

D *9.106 In a particular design of the CMOS op amp of Fig. 9.37 the designer wishes to investigate the effects of increasing the W/L ratio of both Q1 and Q2 by a factor of 4. Assuming that all other ...

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