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venkyelectrical
Asked: 2022-03-19T06:29:17+00:00 In:

16.13 It is required to design a CMOS logic circuit that realizes a three-input, even-parity checker. Specifically, the output Y is to be low when an even number (0 or 2) of the inputs A, B, and C are high. (a)Give the Boolean function images. (b)Sketch a PDN directly from the expression for images. Note that it requires 12 transistors in addition to those in the inverters. (c)From inspection of the PDN circuit, reduce the number of transistors to 10 (not counting those in the inverters). (d)Find the PUN as a dual of the PDN in (c), and hence the complete realization.

16.13 It is required to design a CMOS logic circuit that realizes a three-input, even-parity checker. Specifically, the output Y is to be low when an even number (0 or 2) of the inputs A, B, and C are high.

(a)Give the Boolean function images.
(b)Sketch a PDN directly from the expression for images. Note that it requires 12 transistors in addition to those in the inverters.
(c)From inspection of the PDN circuit, reduce the number of transistors to 10 (not counting those in the inverters).
(d)Find the PUN as a dual of the PDN in (c), and hence the complete realization.

microelectronics by sedra and smith 8th edition chapter 16
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