16.14 Give a CMOS logic circuit that realizes the function of a three-input, odd-parity checker. Specifically, the output is to be low when an odd number (1 or 3) of the inputs are high. Attempt a design with 10 transistors (not counting those in the inverters) in each of the PUN and the PDN.
16.14 Give a CMOS logic circuit that realizes the function of a three-input, odd-parity checker. Specifically, the output is to be low when an odd number (1 or 3) of the inputs are high. Attempt a design with 10 transistors (not counting those in the inverters) in each of the PUN and the PDN.
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