18.35 In a particular dynamic memory chip, CS = 30 fF, the bit-line capacitance per cell is 0.5 f F, and bit-line control circuitry involves 12 fF. For a 1-Mbit-square array, what bit-line signals result when a stored 1 is read? When a stored 0 is read? Assume that VDD = 1.0 V.
18.35 In a particular dynamic memory chip, CS = 30 fF, the bit-line capacitance per cell is 0.5 f F, and bit-line control circuitry involves 12 fF. For a 1-Mbit-square array, what bit-line signals result when a stored 1 is read? When a stored 0 is read? Assume that VDD = 1.0 V.
VenkyelectricalEnlightened
1 Answer