2. Lag Compensator Design Using Root-Locus Consider the unity feedback system in Figure 1 for G(s)— 1 s(s +3)(s + 6) Design a lag compensation to meet the following specifications: • The step response settling time is to be less than 5 sec • The step response overshoot is to be less than 17%. • The steady-state error to a unit ramp input must not exceed 10%. Dynamic specifications (overshoot and settling time) can be met using proportional feedback, but a lag compensator is needed to reduce steady-state error. Put the lag filter pole close to origin: use: p = 0.01, and fund determine the zero. Hint: Use the steady-state error requirement to establish a first relationship between the lag compensator gain K and zero z. Then, use the magnitude condition to obtain a second equation relating K and z. You have two equations to determine two unknowns: substitute the first equation into the second to find K and use the first equation again to fmd z.