D *1.77 A designer wishing to lower the overall upper 3-dB frequency of a three-stage amplifier to 5 kHz considers shunting one of two nodes to ground with a capacitor: Node A, at the output of the first stage, or Node B, at the output of the second stage. While measuring the overall frequency response of the amplifier, she connects a capacitor of 1 nF, first to node A and then to node B, lowering the 3-dB frequency from 3 MHz to 200 kHz and 40 kHz, respectively.
If she knows that each amplifier stage has an input resistance of 100 kΩ, what output resistance must the driving stage have at node A? At node B? What capacitor value should she connect to which node to solve her design problem most economically?
0.8 k; 3.98 k; 8 nF at node B