D 7.93 Using the circuit topology displayed in Fig. 7.50(e), arrange to bias the NMOS transistor at ID = 0.2 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, Vt = 0.7 V, λ = 0, and kn = 5 mA/V2. Use a gate-bias resistor of 10 MΩ. Specify RS and RD to two significant digits.
D 7.93 Using the circuit topology displayed in Fig. 7.50(e), arrange to bias the NMOS transistor at ID = 0.2 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, Vt = 0.7 V, λ = 0, and kn = 5 mA/V2. Use a gate-bias resistor of 10 MΩ. Specify RS and RD to two significant digits.
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