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Microelectronics by Sedra and Smith 8th edition Chapter 2
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2.39 Design an op-amp circuit to provide an output vO = −[2v1 + (v2/2)]. Choose the lowest possible values of resistors for which the input current (from each input signal source) does not exceed 50 µA for 1-V input signals.
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2.38 A weighted summer circuit using an ideal op amp as shown in Fig. 2.10 has three inputs using 20- kΩ resistors and a feedback resistor of 50 kΩ. A signal v1 is connected to two of the inputs while a signal v2 is connected to the third. Express vO in terms of v1 and v2. If v1 = 1 V and v2 = −1 V, what is vO?
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D 2.37 Design the circuit shown in Fig. P2.37 to have an input resistance of 100 kΩ and a gain that can be varied from −1 V/V to −100 V/V using the 100- kΩ potentiometer R4. What voltage gain results when the potentiometer is set exactly at its middle value?
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D2.20Design a differentiator to have a time constant of 10−2 s and an input capacitance of 0.01 µF. What is the gain magnitude and phase of this circuit at 10 rad/s, and at 103 rad/s? In order to limit the high-frequency gain of the differentiator circuit to 100, a resistor is added in series with the capacitor. Find the required resistor value. C = 0.01 µF; R = 1 MΩ; at ω = 10 rad/s: |Vo/Vi| = 0.1 V/V and ϕ = −90°; at ω = 1000 rad/s: |Vo/Vi| = 10 V/V and ϕ = −90°; 10 kΩ
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D2.19Use an ideal op amp to design an inverting integrator with an input resistance of 10 kΩ and an integration time constant of 10−3 s. What is the gain magnitude and phase angle of this circuit at 10 rad/s and at 1 rad/s? What is the frequency at which the gain magnitude is unity? R = 10 kΩ, C = 0.1 µF; at ω = 10 rad/s: |Vo/Vi| = 100 V/V and ϕ = +90°; at ω = 1 rad/s: |Vo/Vi| = 1000 V/V and ϕ = +90°; 1000 rad/s
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2.17Consider the instrumentation amplifier of Fig. 2.20(b) with a common-mode input voltage of +5V (dc) and a differential input signal of 10-mV-peak sine wave. Let (2R1) = 1 kΩ, R2 = 0.5 MΩ, and R3 = R4 = 10 kΩ. Find the voltage at every node in the circuit. vI1 = 5 − 0.005 sin ωt; vI2 = 5 + 0.005 sin ωt; v−(op amp A1) = 5 − 0.005 sin ωt; v−(op amp A2) = 5 + 0.005 sin ωt; vO1 = 5 − 5.005 sin ωt; vO2 = 5 + 5.005 sin ωt; v− (A3) = v+(A3) = 2.5 + 2.5025 sin ωt; vO = 10.01 sin ωt (all in volts)
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D2.16Find values for the resistances in the circuit of Fig. 2.16 so that the circuit behaves as a difference amplifier with an input resistance of 20 kΩ and a gain of 10. R1 = R3 = 10 kΩ; R2 = R4 = 100 kΩ
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2.14It is required to connect a transducer having an open-circuit voltage of 1 V and a source resistance of 1 MΩ to a load of 1- kΩ resistance. Find the load voltage if the connection is done (a) directly, and (b) through a unity-gain voltage follower. (a) 1 mV; (b) 1 V
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D 2.14 Design an inverting op-amp circuit for which the gain is −5 V/V and the total resistance used is 6 kΩ. R1 = 1 kΩ; R2 = 5 kΩ;
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D 2.13 Given an ideal op amp, what are the values of the resistors R1 and R2 to be used to design amplifiers with the closed-loop gains listed below? In your designs, use at least one 10- kΩ resistor and another equal or larger resistor. (a)−1 V/V (b)−10 V/V (c)−20 V/V (d)−0.5 V/V
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SIM 2.12 For ideal op amps operating with the following feedback networks in the inverting configuration, what closed-loop gain results? (a)R1 = 10 kΩ, R2 = 20 kΩ (b)R1 = 10 kΩ, R2 = 100 kΩ (c)R1 = 10 kΩ, R2 = 5 kΩ (d)R1 = 100 kΩ, R2 = 5 MΩ (e)R1 = 100 kΩ, R2 = 0.5 MΩ (a) −2 V/V; (b) −10 V/V; (c) −0.5 V/V; (d) −50 V/V; (e) −5 V/V
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D 2.15 Using the circuit of Fig. 2.5 and assuming an ideal op amp, design an inverting amplifier with a gain of 26 dB having the largest possible input resistance under the constraint of having to use resistors no larger than 100 kΩ. What is the input resistance of your design?
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2.50 Derive an expression for the voltage gain, vO/vI, of the circuit in Fig. P2.50.
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October 6, 2021
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D2.8Use the idea presented in Fig. 2.11 to design a weighted summer that provides
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D2.11Design a noninverting amplifier with a gain of 2. At the maximum output voltage of 10 V the current in the voltage divider is to be 10 µA. R1 = R2 = 0.5 MΩ
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2.9Use the superposition principle to find the output voltage of the circuit shown in Fig. E2.9
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D2.4Use the circuit of Fig. 2.5 to design an inverting amplifier having a gain of −10 and an input resistance of 100 kΩ. Give the values of R1 and R2. R1 = 100 kΩ; R2 = 1 MΩ
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D*2.127 In designing with op amps one has to check the limitations on the voltage and frequency ranges of operation of the closed-loop amplifier, imposed by the op-amp finite bandwidth (ft), slew rate (SR), and output saturation (Vomax). This problem illustrates the point by considering the use of an op amp with ft = 20 MHz, SR = 10 V/µs, and Vomax = 10 V in the design of a noninverting amplifier with a nominal gain of 10. Assume a sine-wave input with peak amplitude Vi. (a)If Vi = 0.5 V, what is the maximum frequency before the output distorts? (b)If f = 200 kHz, what is the maximum value of Vi before the output distorts? (c)If Vi = 50 mV, what is the useful frequency range of operation? (d)If f = 50 kHz, what is the useful input voltage range? (a) 318.3 kHz; (b) 0.795 V; (c) 2 MHz; (d) 1 V
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October 3, 2021
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2.126 For an amplifier having a slew rate of 40 V/µs, what is the highest frequency at which a 2-V peak-to-peak sine wave can be produced at the output? 6.37 MHz
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2.125 An inverting amplifier with a gain of −5 V/V and input resistance 20 kΩ uses an op amp with a slew rate of 1 V/µs, maximum output current of ±1 mA, and ft = 3 MHz. (a)At what frequency will the amplifier gain drop by 1 dB? (b)At the frequency specified in (a), what is the maximum amplitude sinusoid for which the amplifier will avoid slew rate limiting? (c)Under the conditions described in parts (a) and (b), what is the largest capacitive load that can be driven while staying within the maximum output current limits?
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