SIM 8.72 A CMOS cascode amplifier such as that in Fig. 8.32(a) has identical CS and CG transistors that have W/L = 5.4 µm/0.36 µm and biased at I = 0.2 mA. The circuit is fabricated in the 0.18-µm process specified in Table K.1. At what value of RL does the gain become –100 V/V? What is the voltage gain of the common-source stage?