D 17.32 A logic-circuit family with zero static power dissipation normally operates at VDD = 1.8 V. To reduce its dynamic power dissipation, operation at 1.2 V is considered. It is found, however, that the currents available to charge and discharge load capacitances also decrease. If current is (a) proportional to VDD or (b) proportional to what reductions in maximum operating frequency do you expect in each case? What fractional change in delay–power product do you expect in each case?
D 17.32 A logic-circuit family with zero static power dissipation normally operates at VDD = 1.8 V. To reduce its dynamic power dissipation, operation at 1.2 V is considered. It is found, however, that the currents available to charge and discharge load capacitances also decrease. If current is (a) proportional to VDD or (b) proportional to what reductions in maximum operating frequency do you expect in each case? What fractional change in delay–power product do you expect in each case?
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